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电信和无线电工程
SJR: 0.202 SNIP: 0.2 CiteScore™: 0.23

ISSN 打印: 0040-2508
ISSN 在线: 1943-6009

卷:
卷 78, 2019 卷 77, 2018 卷 76, 2017 卷 75, 2016 卷 74, 2015 卷 73, 2014 卷 72, 2013 卷 71, 2012 卷 70, 2011 卷 69, 2010 卷 68, 2009 卷 67, 2008 卷 66, 2007 卷 65, 2006 卷 64, 2005 卷 63, 2005 卷 62, 2004 卷 61, 2004 卷 60, 2003 卷 59, 2003 卷 58, 2002 卷 57, 2002 卷 56, 2001 卷 55, 2001 卷 54, 2000 卷 53, 1999 卷 52, 1998 卷 51, 1997

电信和无线电工程

DOI: 10.1615/TelecomRadEng.v78.i12.80
pages 1107-1115

LOW POWER ARCHITECTURE OF 8BIT-9BIT ENCODER AND 9BIT-8BIT DECODER USING CLOCK GATING SCHEME

H. Sh. Mogheer
University of Diyala, Baquba, Diyala Province, P.O. Box:(32001), Iraq
Kh. Kh. Hasan Al-jumaili
Tikrit University, Tikrit, Salahadin Province, P.O. Box:(42), Iraq
K. J. Ali
Tikrit University, Tikrit, Salahadin Province, P.O. Box:(42), Iraq

ABSTRACT

Clock gating is an efficient technique for reducing power consumption in digital design. It saves more power by partitioning the main clock and distributing the clock to the logic blocks only when there is a need for those blocks to be activated. The proposed architecture used to control the encoder and decoder modules. In this paper a clock gated 8bit-9bit encoder and 9bit-8bit decoder design was executed. The proposed design with gated clock using negative latch clock gating improves power consumption without degrading the design performance. The suggested scheme was achieved 32.18% reduction in power consumption. Encoder and decoder module was executed by using Application-Specific Integrated Circuit (ASIC) design methodology. In order to execute design architecture, 130 nm technology libraries were used for ASIC implementation. The construction of coding and decoding process has been created using Verilog HDL language to cover all the functions. In addition, the simulations are carried out by using ModelSim-Altera 10.3c (Quartus II 14.1) in 130 nm technology.

REFERENCES

  1. Srinivasan, Nandita, et al., (2015) Power reduction by clock gating technique, Procedia Technology, 21, pp. 631-635.

  2. Kumar, Nitin, and Manoj Kumar, (2010) Design of Low Power and High-Speed CMOS Phase Frequency Detector for a PLL, Advances in Signal Processing and Communication, Springer, Singapore, pp. 529-540.

  3. Agarwal, Madhavika, Ria Pathak, and Sophy, P., (2019) Low Power Implementation of a RISC Machine Using Clock Gating Technique.

  4. Khorasani, V., Vahdat, B.V., and Mortazavi, M., (2012) Design and implementation of floating point ALU on a FPGA processor, IEEE International Conference on Computing, Electronics and Electrical Technologies (ICCEET), pp. 772-776.

  5. Dias, W.R.A. and Moreno, E.D., (2012) Code Compression in ARM Embedded Systems using Multiple Dictionaries, IEEE 15th International Conference on Computational Science and Engineering, pp. 209-214.

  6. Beak, S., Van Hieu, B., Park, G., Lee, K., and Jeong, T., (1999) A new binary tree algorithm implementation with Huffman decoder on FPGA, Digest of Technical Papers International Conference on Consumer Electronics (ICCE), pp. 437-438.

  7. Maan Hameed, Khmag, A., Rokhani, F.Z., and Ramli, A.R., (2015) VLSI Implementation of Huffman Design Using FPGA with a Comprehensive Analysis of Power Restrictions, International Journal of Advanced Research in Computer Science and Software Engineering (IJARCSSE), 5(6), pp. 49-54.

  8. Sankar, Sivaneswaran, et al., (2017) Considerations for Static Energy Reduction in Digital CMOS ICs Using NEMS Power Gating, IEEE Transactions on Electron Devices, 64(3), pp. 1399-1403.

  9. Yang, Giyoung and Taewhan Kim, (2018) Design and algorithm for clock gating and flip-flop co-optimization, IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

  10. Kulkarn, R. and Kulkarni, S.Y., (2014) Implementation of Clock Gating Technique and Performing Power Analysis for Processor Engine (ALU) in Network Processors, International Conference on Electronics and Communication System (ICECS -2014), pp.1-6.


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