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Telecommunications and Radio Engineering

Publicou 12 edições por ano

ISSN Imprimir: 0040-2508

ISSN On-line: 1943-6009

SJR: 0.185 SNIP: 0.268 CiteScore™:: 1.5 H-Index: 22

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LOW POWER ARCHITECTURE OF 8BIT-9BIT ENCODER AND 9BIT-8BIT DECODER USING CLOCK GATING SCHEME

Volume 78, Edição 12, 2019, pp. 1107-1115
DOI: 10.1615/TelecomRadEng.v78.i12.80
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RESUMO

Clock gating is an efficient technique for reducing power consumption in digital design. It saves more power by partitioning the main clock and distributing the clock to the logic blocks only when there is a need for those blocks to be activated. The proposed architecture used to control the encoder and decoder modules. In this paper a clock gated 8bit-9bit encoder and 9bit-8bit decoder design was executed. The proposed design with gated clock using negative latch clock gating improves power consumption without degrading the design performance. The suggested scheme was achieved 32.18% reduction in power consumption. Encoder and decoder module was executed by using Application-Specific Integrated Circuit (ASIC) design methodology. In order to execute design architecture, 130 nm technology libraries were used for ASIC implementation. The construction of coding and decoding process has been created using Verilog HDL language to cover all the functions. In addition, the simulations are carried out by using ModelSim-Altera 10.3c (Quartus II 14.1) in 130 nm technology.

Referências
  1. Srinivasan, Nandita, et al., (2015) Power reduction by clock gating technique, Procedia Technology, 21, pp. 631-635.

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  3. Agarwal, Madhavika, Ria Pathak, and Sophy, P., (2019) Low Power Implementation of a RISC Machine Using Clock Gating Technique.

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  7. Maan Hameed, Khmag, A., Rokhani, F.Z., and Ramli, A.R., (2015) VLSI Implementation of Huffman Design Using FPGA with a Comprehensive Analysis of Power Restrictions, International Journal of Advanced Research in Computer Science and Software Engineering (IJARCSSE), 5(6), pp. 49-54.

  8. Sankar, Sivaneswaran, et al., (2017) Considerations for Static Energy Reduction in Digital CMOS ICs Using NEMS Power Gating, IEEE Transactions on Electron Devices, 64(3), pp. 1399-1403.

  9. Yang, Giyoung and Taewhan Kim, (2018) Design and algorithm for clock gating and flip-flop co-optimization, IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

  10. Kulkarn, R. and Kulkarni, S.Y., (2014) Implementation of Clock Gating Technique and Performing Power Analysis for Processor Engine (ALU) in Network Processors, International Conference on Electronics and Communication System (ICECS -2014), pp.1-6.

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