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The Impact Factor measures the average number of citations received in a particular year by papers published in the journal during the two preceding years. 2017 Journal Citation Reports (Clarivate Analytics, 2018) IF: 1.3 To calculate the five year Impact Factor, citations are counted in 2017 to the previous five years and divided by the source items published in the previous five years. 2017 Journal Citation Reports (Clarivate Analytics, 2018) 5-Year IF: 1.7 The Immediacy Index is the average number of times an article is cited in the year it is published. The journal Immediacy Index indicates how quickly articles in a journal are cited. Immediacy Index: 0.7 The Eigenfactor score, developed by Jevin West and Carl Bergstrom at the University of Washington, is a rating of the total importance of a scientific journal. Journals are rated according to the number of incoming citations, with citations from highly ranked journals weighted to make a larger contribution to the eigenfactor than those from poorly ranked journals. Eigenfactor: 0.00023 The Journal Citation Indicator (JCI) is a single measurement of the field-normalized citation impact of journals in the Web of Science Core Collection across disciplines. The key words here are that the metric is normalized and cross-disciplinary. JCI: 0.11 SJR: 0.244 SNIP: 0.521 CiteScore™:: 3.6 H-Index: 14

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DESIGN AND ANALYSIS OF TRI-LAYERED STRAINED CHANNEL DG SHOI FET AT 14 NM

Volume 13, Issue 2, 2022, pp. 61-72
DOI: 10.1615/NanoSciTechnolIntJ.2022039157
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ABSTRACT

Semiconductor device scaling in deep sub-nm scale strained silicon technology-based double-gate (DG) field effect transistors (FETs) with strained channel developed at 14-nm channel length provides a promising substitute in restricting performance degradation beyond 22 nm technology node. The newly designed double-gate field effect transistor on the insulator is comprised of a three-layer structure s-Si/s-SiGe/s-Si, which is directly deployed in the channel region. But the thickness of channel layers is varied to that in the previously designed 22-nm channel length device, which results in mobility enhancement in the channel region. The linear drive current enhancement is measured analytically with incorporation of the effect of strain on mobility of the charge carrier. Due to additional control with two gates in the device, the charge carrier flows from source to drain, experiencing ballistic transport through the short channel. The DG FET with strained channel designed on a 14-nm technology node provides 53.5% enrichment in drain current to that of a 22-nm channel length with acceptable leakage current.

REFERENCES
  1. Badaroglu, M., International Roadmap for Devices and Systems, 2017.

  2. Chaudhry, A. and Kumar, M.J., Investigation of the Novel Attributes of a Fully Depleted Dual-Material Gate SOI MOSFET, IEEE Transact. Electron Dev., vol. 51, no. 9, pp. 1463-1467, 2004.

  3. Fasarakis, N., Tsormpatzoglou, A.H., Tassis, D., Pappas, I., Papathanasiou, K., Bucher, M., Ghibaudo, G.A., and Dimitriadis, C., Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs, IEEE Transact. Electron Dev., vol. 59, no. 7, pp. 1891-1898, 2012.

  4. Faynot, O., Andrieu, F., Weber, O., Fenouillet-Beranger, C., Perreau, P., Mazurier, J., Benoist, T., Rozeau, O., Poiroux, T., Vinet, M., and Grenouillet, L., Planar Fully Depleted SOI Technology: A Powerful Architecture for the 20nm Node and Beyond, 2010 International Electron Devices Meeting, San Francisco, CA, 2010.

  5. Ferain, I., Colinge, C.A., and Colinge, J.P., Multigate Transistors as the Future of Classical Metal-Oxide-Semiconductor Field-Effect Transistors, Nature, vol. 479, no. 7373, pp. 310-316, 2011.

  6. Flachowsky, S., Wei, A., Illgen, R., Herrmann, T., Hontschel, J., Horstmann, M., Klix, W., and Stenzel, R., Understanding Strain-Induced Drive-Current Enhancement in Strained-Silicon n-MOSFET and p-MOSFET, IEEE Transact. Electron Dev., vol. 257, no. 6, pp. 1343-1354, 2010.

  7. Haensch, W., Nowak, E.J., Dennard, R.H., Solomon, P.M., Andres, B., Dokumaci, O.H., Kumar, A., Johnson, J.B., and Fischetti, M.V., Silicon CMOS Devices beyond Scaling, IBM J. Res. Dev., vol. 50, no. 4.5, pp. 339-361, 2006.

  8. Huang, C.H. and Li, Y., Electrical Characteristic of InGaAs Multiple-Gate MOSFET Devices, 2015 Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD), Washington, DC, pp. 357-360, 2015.

  9. Khiangte, L. and Dhar, R.S., Development of Tri-Layered s-Si/s-SiGe/s-Si Channel Heterostructure-on-Insulator MOSFET for Enhanced Drive Current, Phys. Status Solidi B, vol. 255, no. 8, Article ID 1800034, 2018.

  10. Kim, S.D., Park, C.M., and Woo, J.C.S., Advanced Model and Analysis for Series Resistance in sub-100 nm CMOS Including Poly Depletion and Overlap Doping Gradient Effect, Int. Electron Devices Meeting Technical Digest. IEDM, Washington, DC, pp. 723-726, 2000.

  11. Kumar, K., Khiangte, L., and Dhar, R.S., Design of DG MOSFET with Tri-Layered Strained Silicon Channel, J. Phys. Conf. Ser., vol. 1478, p. 012002, 2020.

  12. Li, G., Yao, K., and Gao, G., Strain-Induced Enhancement of Thermoelectric Performance of TiS2 Monolayer Based on First-Principles Phonon and Electron Band Structures, Nanotechnology, vol. 29, no. 1, p. 015204, 2017.

  13. Lime, F., Iniguez, B., and Moldovan, O., Quasi-Two-Dimensional Compact Drain-Current Model for Undoped Symmetric Double-Gate MOSFETs Including Short-Channel Effects, IEEE Transact. Electron Dev, vol. 55, no. 6, pp. 1441-1448, 2008.

  14. Lu, H., Lu, W.Y., and Taur, Y., Effect of Body Doping on Double-Gate MOSFET Characteristics, Semiconduct. Sci. Technol., vol. 23, no. 1, p. 015006, 2007.

  15. Lundstrom, M.S., On the Mobility versus Drain Current Relation for a Nanoscale MOSFET, IEEE Electron Dev. Lett., vol. 22, no. 6, pp. 293-295, 2001.

  16. Mohapatra, S.K., Pradhan, K.P., Sahu, P.K., and Kumar, M.R., The Performance Measure of GS-DG MOSFET: An Impact of Metal Gate Work Function, Adv. Nat. Sci. Nanosci. Nanotechnol., vol. 5, no. 2, Article ID 025002, 2014.

  17. Monga, U. and Fjeldly, T.A., Compact Subthreshold Current Modeling of Short-Channel Nanoscale Double-Gate MOSFET, IEEE Transact. Electron Dev., vol. 56, no. 7, pp. 1533-1537, 2009.

  18. Ning, T.H., A Perspective on the Theory of MOSFET Scaling and Its Impact, IEEE Solid-State Circuits Soc. Newslett., vol. 12, no. 1, pp. 27-30, 2007.

  19. Oh, S.H., Monroe, D., and Hergenrother, J.M., Analytic Description of Short-Channel Effects in Fully-Depleted Double-Gate and Cylindrical, Surrounding-Gate MOSFETs, IEEE Electron Dev. Lett., vol. 21, no. 9, pp. 445-447, 2000.

  20. Pavanello, M.A., Martino, J.A., Dessard, V., and Flandre, D., An Asymmetric Channel SOI nMOSFET for Reducing Parasitic Effects and Improving Output Characteristics, Electrochem. Solid State Lett., vol. 3, no. 1, p. 50, 1999.

  21. Sharma, R.K., Dimitriadis, C.A., and Bucher, M., A Comprehensive Analysis of Nanoscale Single- and Multi-Gate MOSFETs, Microelectron. J., vol. 52, pp. 66-72, 2016.

  22. Sharma, R.K., Gupta, M., and Gupta, R.S., TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFET, IEEE Transact. Electron Dev., vol. 58, no. 9, pp. 2936-2943, 2011.

  23. Shin, C., Kim, J.K., and Yu, H.-Y., Threshold Voltage Variation-Immune FinFET Design with Metal-Interlayer-Semiconductor Source/Drain Structure, Curr. Appl. Phys., vol. 16, no. 6, pp. 618-622, 2016.

  24. Skotnicki, T., Hutchby, J.A., King, T.J, Wong, H-SP., and Boeuf, F., The End of CMOS Scaling: Toward the Introduction of New Materials and Structural Changes to Improve MOSFET Performance, IEEE Circuits Dev. Mag., vol. 21, no.1, pp. 16-26, 2005.

  25. Zhang, Q., Wang, C., Wang, H., Schnabel, C., Park, D.G., Scott, K., and Leobandung, E., Experimental Study of Gate-First FinFET Threshold-Voltage Mismatch, IEEE Transact. Electron Dev., vol. 61, no. 2, pp. 643-646, 2014.

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